With the development of advanced technology today, there are more and more things to fight, especially after 5nm, whether it is equipment, materials, cost, or even the process itself, a qualitative leap will occur.


FinFET逐渐失效之后,GAA逐渐登上历史舞台。 For example, in the process of promoting the development of Moore's Law, EUV manufacturing equipment is particularly important; after FinFET gradually fails, GAA gradually enters the stage of history. As long as Moore's Law does not die, the battle for the process will never stop. In the past few years, Samsung and TSMC have been fiercely heated, and Intel has secretly saved its energy. Recently, ASML "misreads" Intel's process roadmap at the IEDM conference, and it has attracted readers to face great interest in the future development of wafer manufacturers.


Below we look at the process roadmaps of the three major wafer fabs, TSMC, Samsung and Intel.


A closer look at the three roadmaps


Intel believes in Moore's Law


不过近些时候他们似乎已经重回轨道。 As we all know, Intel has delayed for many years in 10nm process technology, but in recent times they seem to be back on track. Relevant reports indicate that Intel is trying to restore the usual two-year pace and has begun to accelerate the 10nm process. At the IEDM conference, Martin van den Brink, CEO of ASML, also deliberately expressed his views on Intel's process roadmap from the perspective of equipment suppliers.


上图为ASML在英特尔原图的基础上增加了节点 Legend: The above picture shows ASML adding nodes on the basis of Intel's original picture


First of all, we need to emphasize that according to the report of ANANDTECH, the node evolution ppt (above) demonstrated by ASML is a revision of the content released by Intel in September this year. ASML added animation on the slide to make the bottom line of the date Corresponds to a specific node. Intel's original slide did not specify which node was in which year.



Intel predicts that its manufacturing process node technology will have a two-year cycle, starting from 10nm in 2019 to 7nm EUV in 2021, and then in each of 2023, 2025, 2027, and 2029 there will be a basic New node. The last node is called "1.4nm" by ASML, which is also the first time that a 1.4nm process has been mentioned by a manufacturer.


But according to Intel, between each process node, there will be iterative + and ++ versions in order to extract performance from each process node. The only exception is 10nm, because it is already on 10nm +, so 10nm ++ will be pushed next year, and 10nm +++ will be pushed in 2021. Intel believes that they can do this in a one-year cycle, but there are overlapping teams to ensure that a complete process node can overlap with another node.


At the IEDM conference, ASML also mentioned backward porting. What is backward migration? This is the chip's ability to consider a process node during design, but it may need to be redesigned on an older "++" version of the process node in the same time due to the delay. Although Intel states that they are separating the chip design from the process node technology, to a certain extent, in order to begin the layout in silicon, a commitment must be made to the process node.



The above figure shows that Intel will allow such a workflow. Any first-generation 7nm design can be ported back to 10nm +++. In the future, Intel's 5nm will come from the basic 7nm design and 3nm will come from 5nm. We have seen that Intel's 10nm takes a long time to complete, so it is expected that Intel will update + once a year and update the main process technology node once every two years, which will be a very optimistic and positive rhythm strategy.


ANANDTECH also reported that from the above we can also see that Intel still believes in Moore's Law, just don't ask how much it will cost.


TSMC's process nodes frequently win


TSMC's process research and development speed is very fast in the industry, especially the mastery of EUV process. In the field of wafer foundry, TSMC is undoubtedly the absolute king, and the layout of its process roadmap is also quite compact. At present, its 5nm countdown to mass production, 3nm progresses smoothly, and then it is 2nm.


wikichip Source: wikichip


Overall, according to a wikichip report, TSMC's 10-nm node (N10) node is considered a short-lived node and is mainly used for yield-learning. TSMC sees their 7-nanometer node as the most advanced logic technology currently available. With the exception of a few key customers, most of TSMC's customers are said to have switched directly from N16 to N7. When going from N16 to N7, N7 provides 3.3 times the density of routing gates and a speed improvement or reduction of 65% of power by about 35-40%.


Based on N7, TSMC has launched N7P and N7 +. N7P and N7 + cannot be confused. N7P is an optimized, DUV-based process that uses the same design rules and is fully compatible with N7. N7P introduces FEOL and MOL optimizations. It is said that the performance is increased by 7% at the same power, and the performance is reduced by 10% at the same speed. N7 + is their first batch of process technology that uses EUV in certain critical layers. Compared to their N7 process, the density of N7 + is increased by about 1.2 times. It is said that N7 + can provide 10% higher performance at equal power, or 15% power reduction at equal power. It seems that N7 + is better than N7P.


The EUV of N6 is equivalent to N7. It plans to use more EUV layers than N7 +. It is both a design rule and an IP compatible with N7, and is the main migration path for most customers. The design of N7 can be re-pasted to N6, using EUV mask and fidelity improvements, or re-implementing, using poly over diffusion edge (PODE) and continuous diffusion (CNOD) standard cell abutment rules, which is said to provide an additional 18 % Density improvement. It is worth emphasizing that N6 is unique in that it will enter the risk production stage early next year and reach its peak at the end of 2020. This means it will tilt after N5. Therefore, TSMC stated that N6 is based on N7 + and N5 EUV.


TSMC's 5nm process is the next "complete node" after N7 . The N5 uses both deep ultraviolet (DUV) and extreme ultraviolet (EUV) lithography. N5 can use EUVL on 14 layers to significantly increase density, and N7 + uses EUVL on 4 non-critical layers, which can be said to be a tangible improvement.


N5 technology will allow chip developers to reduce the chip area of their designs by about 45% and increase transistor density by about 1.8 times. It can also increase frequency by 15% at the same complexity and power or reduce power consumption by 20% at the same frequency and complexity. N5 entered risk production in the first quarter of this year, and they expect this process to accelerate in the first half of 2020. Like N7, there will be two types of N5-mobile client and high-performance computing. N5 is planned as a long-lived node and it is expected to grow faster than N7 in terms of revenue.


Like their 7-nanometer process, TSMC will provide an optimized version of their N5 process, called the N5 Performance Enhanced Edition (N5P). This process uses the same design rules and is fully compatible with the N5. Through FEOL and MOL optimization, the performance of N5P is 7% higher than that of N5 at the same power, and the performance of N5P is reduced by 15% at the same power. They are a little vague about N5P's timeline, but they sometimes hint at the end of 2020 or early 2021.


TSMC said that its 3nm process is progressing well and customers have already participated in it. TSMC announced that 3nm is a new node, not an extension of 5nm. In addition, N3 is expected to be launched around 2022.


Samsung's four major nodes


Compared to TSMC and Intel, Samsung's roadmap is the least risky.


According to the latest report from wikichip, Samsung still adheres to the strategy they outlined a few years ago-producing four main nodes, namely 14nm, 10nm, 7nm and 3nm. Because each evolution node is highly incremental, usually only a single change is introduced. This allows them to reduce the risk of new nodes by stripping out some previously introduced extension boosters and adding them on subsequent nodes. However, the disadvantage of this is that the gap between Samsung's main nodes is quite large. In terms of PPA, they lag behind TSMC.



For example, the first modification in this year's roadmap was the insertion of a new 6-nanometer node. Another change is the removal of 4LPP nodes, leaving only 4LPE on the roadmap. Finally, Samsung renamed 3GAAE and 3GAAP to 3GAE and 3GAP.


As can be seen from the roadmap, Samsung is mainly working on 7LPP, of which 6LPP is an improved version of Samsung 7LPP, with higher transistor density and lower power, but it can reuse the IP originally designed for 7LPP. Then there is 5LPE. Samsung plans to use 5nm as the second-generation EUV process.


But 5LPE does introduce some new enhancements. According to wikichip estimates, the density of Samsung's 5 nm node UHD unit has reached close to 130 MTr / mm2, which is the first Samsung node to surpass Intel's 10 nm node and TSMC's 7 nm node. Samsung is expected to launch the first chips using its 5LPE technology in the second half of this year, and mass production is expected in the first half of 2020.


The peak of Samsung's 7LPP evolution will be the company's 4LPE technology (probably 4LPP is not in the latest Samsung roadmap). Samsung will complete its development in the second half of this year, so it is expected that the first batch of tapes will be launched in 2020 and mass-produced in 2021, the ANANDTEC report states.


The 3nm node is really happening, because Samsung will give up FinFETs to GAA transistors starting from 3nm. The first generation is the 3GAE process, and there is an optimized version of the 3GAP process, which is still being optimized and improved.


EUV lithography machine is a key part


During the evolution of these three manufacturers, EUV lithography machines are a key link, and TSMC, Samsung and Intel all plan to adopt EUV in their production roadmaps. But TSMC is undoubtedly a leader in EUV lithography. In October this year, TSMC announced that its 7nm plus (N7 +) node has become the industry's first commercial EUV technology. N7 + is their first batch of process technology that uses EUV in certain critical layers.


Arete Research senior analyst Jim Fontanelli also said that TSMC is a leader in EUV, whether it is the tools used or ordered, the number of commercial EUV wafers produced, or the integration of EUV into their future roadmap.


According to the data released by Takuya, TSMC's 7nm (including EUV) wafer production capacity is estimated to be 100,000-110,000 wafers / month this year. AMD、海思、苹果、高通、赛灵思、英伟达等。 The main customers are: AMD, Hisilicon, Apple, Qualcomm, Xilinx, Nvidia and so on. This year's Samsung 7nm LPP (EUV) process wafer capacity is about 10,000 pieces / month, only about 1/10 of TSMC.


Samsung's layout on EUV is also very early. As early as October 2018, Samsung began to mass produce chips using its 7nm EUV process technology. In April this year, Samsung announced that it had completed the development of its first generation of 5nm manufacturing process (5LPE), which uses extreme ultraviolet lithography (EUVL), which can provide significant advantages compared to the 7nm process (called 7LPP). Performance, power and area advantages.


Samsung predicts that 5nm will become its main EUVL node by 2020, which may be because the technology can provide numerous benefits for multiple applications, and Samsung's EUV yield will be higher, mainly because Samsung is in Huacheng After the EUV production line is built, it will have more EUV production capacity in the next few months. The plant will cost 4.615 billion U.S. dollars and it is expected to begin mass production in 2020.



Over the years, Intel has been the most active in EUV research. At the recent IEDM conference, 5nm was listed as the node of 2023 in Intel's process route disclosed by ASML CEO Martin van den Brink. At about this time, ASML will start selling its "High NA" EUV machine. To help Intel better define the path during the manufacturing process.


他们在确信EUV已经准备好投入生产之前不会宣布。 Dan Hutcheson, CEO of VLSI Research, previously stated: "In these three companies, Intel is a mystery because it has no sales reason to promote what it is doing, and Intel has always been good at pushing its lithium tools to a node. .They won't announce until they are convinced that EUV is ready for production. "


The choice of future transistors


After entering the semiconductor node below 32nm, each step of the semiconductor process is extremely difficult. The first is the failure of the planar transistor. From the perspective of technological development, after the size of the planar transistor is reduced to 22nm, the barrier tunneling effect causes current leakage, and leakage current control will become very difficult. FinFET is undoubtedly a huge success. Although FinFET was invented more than 10 years ago, it was first commercially launched by Intel, Samsung, TSMC and other companies on the 22nm node in 2011. Since then, in the final stages of Moore's Law calibration, it has become the workhorse of cutting-edge silicon logic.


But with the reduction in size, after 5nm and 3nm, FinFETs are not capable of this task. The size of FinFET itself has been reduced to the limit. Whether it is the fin distance, short channel effect, or leakage and material limits, the transistor Manufacturing is more difficult, and even the physical structure cannot be completed.


At this time, new transistors such as GAA, two-dimensional transistors, and nanochip transistors have become new directions for consideration in the industry. Among them, GAA technology has been favored by Samsung, TSMC and Intel, and some have begun trial production.


Planar transistors and finFETs and nanosheet FETs. 三星 Source: Samsung


In terms of GAA, Samsung has the most outstanding performance. Samsung believes that 3 nanometers is its next major process technology node. It plans to use Nano-based Gate-All-Around MBCFET transistors for its own 3nm (3GAAE) process technology. Nodes that will use the GAA process. In April of this year, Samsung released its first process design kit (PDK) -version 0.1 for its 3nm GAA process, with mass production expected in 2021.


Handel Jones, CEO of International Business Strategy, said that due to Samsung's huge investment in research and development of advanced materials including graphene, Samsung's GAA lead in TSMC is about one year. “三星在3纳米GAA中处于领先地位,其主要优势是由于内部可获取纳米片结构材料。 Jones said: "Samsung is a leader in 3nm GAA, and its main advantage is due to the internal availability of nanosheet structural materials. "


Although TSMC has not directly provided official instructions like Samsung, it has also started research and development and trial production of GAA-related technologies. TSMC plans to launch a version of its GAA technology at the 5nm node, but has not announced a target date for putting the technology into production. According to industry insiders, TSMC has also completed the production of wrap-around gate transistors, but it uses circular fins, which have a typical size that is 30% smaller than existing processes.


Two-dimensional transistors are also seen as one of the best candidates to continue Moore's Law. According to the analysis of Nature's scientific research report, because three-dimensional transistors generally face the same problem, it is generally difficult for electrons to migrate in the channel of nanometer thickness, and defects on the surface of the channel will also cause charge scattering and slow down the flow of electrons. The two-dimensional material of the monoatomic layer is expected to further shrink the transistors. Because their "vertical" dimensions are limited and the surface is flat and free of defects, the electrons are not easy to scatter and the charges can flow relatively freely.


The IEEE SPECTRUM report states that nanochip transistors are the next, and perhaps the last, step in Moore's Law . Author Peide Ye wrote in the article that the Nanosheet device is planned for 3 nanometer nodes in 2021 . In 2006, engineers at CEA-Leti in France proposed using a stack of thin silicon plates to connect power and drain pipes instead of a stack of nanowires. The idea is to increase the channel width in a smaller transistor while maintaining tight control of leakage current, thereby providing a device with better performance and lower power.


IBM further studied this concept in 2017, showing that transistors made from stacked nanoflakes actually provide more Weff than FinFETs occupying the same chip area. Simultaneously stacked nanosheets also show broad promise for compound semiconductors (such as indium gallium arsenide) and silicon alternatives (such as germanium).


IBM Source: IBM


它恢复了向FinFET过渡时失去的灵活性。 In addition, the design of the nanosheet offers an additional benefit: it restores the flexibility lost during the transition to FinFET. The sheet can be widened to increase current, or it can be made narrow to limit power consumption. IBM Research has stacked them together in sizes ranging from 8 nm to 50 nm.


All in all, stacked nanoflakes seem to be the best way to make transistors in the future. Chip makers already have enough confidence in the technology to include it in their roadmap in the near future. With the integration of high mobility semiconductor materials, nanochip transistors can take us to the distant future that anyone can now foresee. Peide Ye wrote in the article.


As for the development direction of the transistor in the future, the author's point of view is "walk to the water poor, sit and watch the clouds rise."
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